思澈科技软件开发工具包  2.20
Modules
SiFli CMSIS device interface

Modules

 Peripheral_memory_map
 
enum  IRQn {
  NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11,
  UsageFault_IRQn = -10,
  SecureFault_IRQn = -9,
  SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2,
  SysTick_IRQn = -1,
  AON_IRQn = 0,
  BLE_MAC_IRQn = 1,
  DMAC2_CH1_IRQn = 2,
  DMAC2_CH2_IRQn = 3,
  DMAC2_CH3_IRQn = 4,
  DMAC2_CH4_IRQn = 5,
  DMAC2_CH5_IRQn = 6,
  DMAC2_CH6_IRQn = 7,
  DMAC2_CH7_IRQn = 8,
  DMAC2_CH8_IRQn = 9,
  PATCH_IRQn = 10,
  Interrupt11_IRQn = 11,
  USART3_IRQn = 12,
  USART4_IRQn = 13,
  USART5_IRQn = 14,
  Interrupt15_IRQn = 15,
  SPI3_IRQn = 16,
  SPI4_IRQn = 17,
  Interrupt18_IRQn = 18,
  I2C4_IRQn = 19,
  I2C5_IRQn = 20,
  I2C6_IRQn = 21,
  GPTIM3_IRQn = 22,
  GPTIM4_IRQn = 23,
  GPTIM5_IRQn = 24,
  BTIM3_IRQn = 25,
  BTIM4_IRQn = 26,
  Interrupt27_IRQn = 27,
  GPADC_IRQn = 28,
  SDADC_IRQn = 29,
  Interrupt30_IRQn = 30,
  Interrupt31_IRQn = 31,
  TSEN_IRQn = 32,
  PTC2_IRQn = 33,
  LCDC2_IRQn = 34,
  GPIO2_IRQn = 35,
  QSPI4_IRQn = 36,
  Interrupt37_IRQn = 37,
  Interrupt38_IRQn = 38,
  Interrupt39_IRQn = 39,
  Interrupt40_IRQn = 40,
  LPCOMP_IRQn = 41,
  LPTIM2_IRQn = 42,
  LPTIM3_IRQn = 43,
  Interrupt44_IRQn = 44,
  Interrupt45_IRQn = 45,
  LPTIM1_IRQn = 46,
  Interrupt47_IRQn = 47,
  IWDT_IRQn = 48,
  RTC_IRQn = 49,
  DMAC1_CH1_IRQn = 50,
  DMAC1_CH2_IRQn = 51,
  DMAC1_CH3_IRQn = 52,
  DMAC1_CH4_IRQn = 53,
  DMAC1_CH5_IRQn = 54,
  DMAC1_CH6_IRQn = 55,
  DMAC1_CH7_IRQn = 56,
  DMAC1_CH8_IRQn = 57,
  LCPU2HCPU_IRQn = 58,
  USART1_IRQn = 59,
  SPI1_IRQn = 60,
  I2C1_IRQn = 61,
  EPIC_IRQn = 62,
  LCDC1_IRQn = 63,
  I2S1_IRQn = 64,
  I2S2_IRQn = 65,
  EFUSEC_IRQn = 66,
  AES_IRQn = 67,
  PTC1_IRQn = 68,
  TRNG_IRQn = 69,
  GPTIM1_IRQn = 70,
  GPTIM2_IRQn = 71,
  BTIM1_IRQn = 72,
  BTIM2_IRQn = 73,
  USART2_IRQn = 74,
  SPI2_IRQn = 75,
  I2C2_IRQn = 76,
  EXTDMA_IRQn = 77,
  PSRAMC_IRQn = 78,
  SDMMC1_IRQn = 79,
  SDMMC2_IRQn = 80,
  NNACC_IRQn = 81,
  PDM1_IRQn = 82,
  DSIHOST_IRQn = 83,
  GPIO1_IRQn = 84,
  QSPI1_IRQn = 85,
  QSPI2_IRQn = 86,
  QSPI3_IRQn = 87,
  EZIP_IRQn = 88,
  PDM2_IRQn = 89,
  USBC_IRQn = 90,
  I2C3_IRQn = 91,
  Interrupt92_IRQn = 92,
  Interrupt93_IRQn = 93,
  Interrupt94_IRQn = 94,
  Interrupt95_IRQn = 95,
  HCPU2LCPU_IRQn = -1
}
 
typedef enum IRQn IRQn_Type
 
#define __CM33_REV   0x0000U /* Core revision r0p1 */
 
#define __SAUREGION_PRESENT   0U /* SAU regions present */
 
#define __MPU_PRESENT   1U /* MPU present */
 
#define __VTOR_PRESENT   1U /* VTOR present */
 
#define __NVIC_PRIO_BITS   3U /* Number of Bits used for Priority Levels */
 
#define __Vendor_SysTickConfig   0U /* Set to 1 if different SysTick Config is used */
 
#define __FPU_PRESENT   1U /* no FPU present */
 
#define __DSP_PRESENT   1U /* no DSP extension present */
 
#define __ICACHE_PRESENT   1U
 
#define __DCACHE_PRESENT   1U
 
#define MPU_REGION_NUM   12
 
#define CACHE_BASE   0xE0080000
 
#define HPSYS_RCC_BASE   0x40000000
 
#define DMAC1_BASE   0x40001000
 
#define MAILBOX1_BASE   0x40002000
 
#define PINMUX1_BASE   0x40003000
 
#define USART1_BASE   0x40004000
 
#define USART2_BASE   0x40005000
 
#define EZIP_BASE   0x40006000
 
#define EPIC_BASE   0x40007000
 
#define LCDC1_BASE   0x40008000
 
#define I2S1_BASE   0x40009000
 
#define I2S2_BASE   0x4000a000
 
#define HPSYS_CFG_BASE   0x4000b000
 
#define EFUSEC_BASE   0x4000c000
 
#define AES_BASE   0x4000d000
 
#define CRC_BASE   0x4000e000
 
#define TRNG_BASE   0x4000f000
 
#define GPTIM1_BASE   0x40010000
 
#define GPTIM2_BASE   0x40011000
 
#define BTIM1_BASE   0x40012000
 
#define BTIM2_BASE   0x40013000
 
#define WDT1_BASE   0x40014000
 
#define SPI1_BASE   0x40015000
 
#define SPI2_BASE   0x40016000
 
#define EXTDMA_BASE   0x40017000
 
#define PSRAMC_BASE   0x40018000
 
#define NNACC_BASE   0x40019000
 
#define PDM1_BASE   0x4001a000
 
#define PDM2_BASE   0x4001b000
 
#define I2C1_BASE   0x4001c000
 
#define I2C2_BASE   0x4001d000
 
#define DSI_HOST_BASE   0x4001e000
 
#define DSI_PHY_BASE   0x4001f000
 
#define PTC1_BASE   0x40020000
 
#define BUSMON1_BASE   0x40021000
 
#define I2C3_BASE   0x40022000
 
#define HPSYS_AON_BASE   0x40030000
 
#define LPTIM1_BASE   0x40031000
 
#define GPIO1_BASE   0x50000000
 
#define QSPI1_BASE   0x50001000
 
#define QSPI2_BASE   0x50002000
 
#define QSPI3_BASE   0x50003000
 
#define SDMMC1_BASE   0x50004000
 
#define SDMMC2_BASE   0x50005000
 
#define USBC_BASE   0x50006000
 
#define EPIC_RAM_BASE   0x50010000
 
#define LPSYS_RCC_BASE   0x40040000
 
#define DMAC2_BASE   0x40041000
 
#define MAILBOX2_BASE   0x40042000
 
#define PINMUX2_BASE   0x40043000
 
#define PATCH_BASE   0x40044000
 
#define USART3_BASE   0x40045000
 
#define USART4_BASE   0x40046000
 
#define USART5_BASE   0x40047000
 
#define SPI3_BASE   0x40049000
 
#define SPI4_BASE   0x4004a000
 
#define I2C4_BASE   0x4004c000
 
#define I2C5_BASE   0x4004d000
 
#define I2C6_BASE   0x4004e000
 
#define LPSYS_CFG_BASE   0x4004f000
 
#define GPTIM3_BASE   0x40050000
 
#define GPTIM4_BASE   0x40051000
 
#define GPTIM5_BASE   0x40052000
 
#define BTIM3_BASE   0x40053000
 
#define BTIM4_BASE   0x40054000
 
#define WDT2_BASE   0x40055000
 
#define GPADC_BASE   0x40056000
 
#define SDADC_BASE   0x40057000
 
#define LPCOMP_BASE   0x40059000
 
#define TSEN_BASE   0x4005a000
 
#define PTC2_BASE   0x4005b000
 
#define LCDC2_BASE   0x4005c000
 
#define BUSMON2_BASE   0x4005d000
 
#define LPSYS_AON_BASE   0x40070000
 
#define LPTIM2_BASE   0x40071000
 
#define LPTIM3_BASE   0x40072000
 
#define PMUC_BASE   0x4007a000
 
#define RTC_BASE   0x4007b000
 
#define IWDT_BASE   0x4007c000
 
#define GPIO2_BASE   0x50040000
 
#define QSPI4_BASE   0x50041000
 
#define BLE_RFC_BASE   0x50042000
 
#define BLE_PHY_BASE   0x50044000
 
#define BLE_MAC_BASE   0x50050000
 
#define HMAILBOX_BASE   MAILBOX1_BASE
 
#define LMAILBOX_BASE   MAILBOX2_BASE
 
#define USBC_X_BASE   (USBC_BASE)
 
#define hwp_cache   ((CACHE_TypeDef *) CACHE_BASE)
 
#define hwp_hpsys_rcc   ((HPSYS_RCC_TypeDef *) HPSYS_RCC_BASE)
 
#define hwp_lpsys_rcc   ((LPSYS_RCC_TypeDef *) LPSYS_RCC_BASE)
 
#define hwp_dmac1   ((DMAC_TypeDef *) DMAC1_BASE)
 
#define hwp_dmac2   ((DMAC_TypeDef *) DMAC2_BASE)
 
#define hwp_gptim1   ((GPT_TypeDef *) GPTIM1_BASE)
 
#define hwp_gptim2   ((GPT_TypeDef *) GPTIM2_BASE)
 
#define hwp_gptim3   ((GPT_TypeDef *) GPTIM3_BASE)
 
#define hwp_gptim4   ((GPT_TypeDef *) GPTIM4_BASE)
 
#define hwp_gptim5   ((GPT_TypeDef *) GPTIM5_BASE)
 
#define hwp_btim1   ((BTIM_TypeDef *) BTIM1_BASE)
 
#define hwp_btim2   ((BTIM_TypeDef *) BTIM2_BASE)
 
#define hwp_btim3   ((BTIM_TypeDef *) BTIM3_BASE)
 
#define hwp_btim4   ((BTIM_TypeDef *) BTIM4_BASE)
 
#define hwp_epic   ((EPIC_TypeDef *) EPIC_BASE)
 
#define hwp_spi1   ((SPI_TypeDef *) SPI1_BASE)
 
#define hwp_spi2   ((SPI_TypeDef *) SPI2_BASE)
 
#define hwp_spi3   ((SPI_TypeDef *) SPI3_BASE)
 
#define hwp_spi4   ((SPI_TypeDef *) SPI4_BASE)
 
#define hwp_usart1   ((USART_TypeDef *) USART1_BASE)
 
#define hwp_usart2   ((USART_TypeDef *) USART2_BASE)
 
#define hwp_usart3   ((USART_TypeDef *) USART3_BASE)
 
#define hwp_usart4   ((USART_TypeDef *) USART4_BASE)
 
#define hwp_usart5   ((USART_TypeDef *) USART5_BASE)
 
#define hwp_i2c1   ((I2C_TypeDef *) I2C1_BASE)
 
#define hwp_i2c2   ((I2C_TypeDef *) I2C2_BASE)
 
#define hwp_i2c3   ((I2C_TypeDef *) I2C3_BASE)
 
#define hwp_i2c4   ((I2C_TypeDef *) I2C4_BASE)
 
#define hwp_i2c5   ((I2C_TypeDef *) I2C5_BASE)
 
#define hwp_i2c6   ((I2C_TypeDef *) I2C6_BASE)
 
#define hwp_mailbox1   ((MAILBOX_TypeDef *) MAILBOX1_BASE)
 
#define hwp_mailbox2   ((MAILBOX_TypeDef *) MAILBOX2_BASE)
 
#define hwp_hmailbox   ((MAILBOX_TypeDef *) MAILBOX1_BASE)
 
#define hwp_lmailbox   ((MAILBOX_TypeDef *) MAILBOX2_BASE)
 
#define hwp_nnacc   ((NN_ACC_TypeDef *) NNACC_BASE)
 
#define hwp_dsi_host   ((DSI_HOST_TypeDef *) DSI_HOST_BASE)
 
#define hwp_dsi_phy   ((DSI_PHY_TypeDef *) DSI_PHY_BASE)
 
#define hwp_ptc1   ((PTC_TypeDef *) PTC1_BASE)
 
#define hwp_ptc2   ((PTC_TypeDef *) PTC2_BASE)
 
#define hwp_busmon1   ((BUSMON_TypeDef *) BUSMON1_BASE)
 
#define hwp_busmon2   ((BUSMON_TypeDef *) BUSMON2_BASE)
 
#define hwp_ezip   ((EZIP_TypeDef *) EZIP_BASE)
 
#define hwp_efusec   ((EFUSEC_TypeDef *) EFUSEC_BASE)
 
#define hwp_rtc   ((RTC_TypeDef *) RTC_BASE)
 
#define hwp_pmuc   ((PMUC_TypeDef *) PMUC_BASE)
 
#define hwp_qspi1   ((QSPI_TypeDef *) QSPI1_BASE)
 
#define hwp_qspi2   ((QSPI_TypeDef *) QSPI2_BASE)
 
#define hwp_qspi3   ((QSPI_TypeDef *) QSPI3_BASE)
 
#define hwp_qspi4   ((QSPI_TypeDef *) QSPI4_BASE)
 
#define hwp_psramc   ((PSRAMC_TypeDef *) PSRAMC_BASE)
 
#define hwp_lptim1   ((LPTIM_TypeDef *) LPTIM1_BASE)
 
#define hwp_lptim2   ((LPTIM_TypeDef *) LPTIM2_BASE)
 
#define hwp_lptim3   ((LPTIM_TypeDef *) LPTIM3_BASE)
 
#define hwp_hpsys_cfg   ((HPSYS_CFG_TypeDef *) HPSYS_CFG_BASE)
 
#define hwp_lpsys_cfg   ((LPSYS_CFG_TypeDef *) LPSYS_CFG_BASE)
 
#define hwp_i2s1   ((I2S_TypeDef *) I2S1_BASE)
 
#define hwp_i2s2   ((I2S_TypeDef *) I2S2_BASE)
 
#define hwp_pdm1   ((PDM_TypeDef *) PDM1_BASE)
 
#define hwp_pdm2   ((PDM_TypeDef *) PDM2_BASE)
 
#define hwp_crc   ((CRC_TypeDef *) CRC_BASE)
 
#define hwp_trng   ((TRNG_TypeDef *) TRNG_BASE)
 
#define hwp_lcdc1   ((LCD_IF_TypeDef *) LCDC1_BASE)
 
#define hwp_lcdc2   ((LCD_IF_TypeDef *) LCDC2_BASE)
 
#define hwp_extdma   ((EXTDMA_TypeDef *) EXTDMA_BASE)
 
#define hwp_sdmmc1   ((SDMMC_TypeDef *) SDMMC1_BASE)
 
#define hwp_sdmmc2   ((SDMMC_TypeDef *) SDMMC2_BASE)
 
#define hwp_aes_acc   ((AES_ACC_TypeDef *) AES_BASE)
 
#define hwp_gpio1   ((GPIO_TypeDef *) GPIO1_BASE)
 
#define hwp_gpio2   ((GPIO_TypeDef *) GPIO2_BASE)
 
#define hwp_usbc   ((USBC_X_Typedef *) USBC_BASE)
 
#define hwp_pinmux1   ((HPSYS_PINMUX_TypeDef *) PINMUX1_BASE)
 
#define hwp_pinmux2   ((LPSYS_PINMUX_TypeDef *) PINMUX2_BASE)
 
#define hwp_hpsys_aon   ((HPSYS_AON_TypeDef *) HPSYS_AON_BASE)
 
#define hwp_lpsys_aon   ((LPSYS_AON_TypeDef *) LPSYS_AON_BASE)
 
#define hwp_gpadc1   ((GPADC_TypeDef *) GPADC_BASE)
 
#define hwp_sdadc   ((SDADC_TypeDef *) SDADC_BASE)
 
#define hwp_lpcomp   ((LPCOMP_TypeDef *) LPCOMP_BASE)
 
#define hwp_tsen   ((TSEN_TypeDef *) TSEN_BASE)
 
#define hwp_patch   ((PATCH_TypeDef *) PATCH_BASE)
 
#define hwp_ble_rfc   ((BLE_RF_DIG_TypeDef *) BLE_RFC_BASE)
 
#define hwp_ble_phy   ((BLE_PHY_TypeDef *) BLE_PHY_BASE)
 
#define hwp_ble_mac   ((BLE_MAC_TypeDef *) BLE_MAC_BASE)
 
#define hwp_wdt1   ((WDT_TypeDef *) WDT1_BASE)
 
#define hwp_wdt2   ((WDT_TypeDef *) WDT2_BASE)
 
#define hwp_iwdt   ((WDT_TypeDef *) IWDT_BASE)
 
#define hwp_usbc_x   ((USBC_X_Typedef *) USBC_X_BASE))
 
#define USART1   hwp_usart1
 
#define USART2   hwp_usart2
 
#define USART3   hwp_usart3
 
#define USART4   hwp_usart4
 
#define USART5   hwp_usart5
 
#define DMA1   hwp_dmac1
 
#define DMA2   hwp_dmac2
 
#define FLASH1   hwp_qspi1
 
#define FLASH2   hwp_qspi2
 
#define FLASH3   hwp_qspi3
 
#define FLASH4   hwp_qspi4
 
#define SDIO1   hwp_sdmmc1
 
#define SDIO2   hwp_sdmmc2
 
#define SPI1   hwp_spi1
 
#define SPI2   hwp_spi2
 
#define SPI3   hwp_spi3
 
#define SPI4   hwp_spi4
 
#define GPTIM1   hwp_gptim1
 
#define GPTIM2   hwp_gptim2
 
#define GPTIM3   hwp_gptim3
 
#define GPTIM4   hwp_gptim4
 
#define GPTIM5   hwp_gptim5
 
#define BTIM1   hwp_btim1
 
#define BTIM2   hwp_btim2
 
#define BTIM3   hwp_btim3
 
#define BTIM4   hwp_btim4
 
#define LPTIM1   hwp_lptim1
 
#define LPTIM2   hwp_lptim2
 
#define LPTIM3   hwp_lptim3
 
#define TRNG   hwp_trng
 
#define PSRAM   hwp_psramc
 
#define H2L_MAILBOX   ((MAILBOX_CH_TypeDef *)HMAILBOX_BASE)
 
#define HMUTEX_CH1   ((MUTEX_CH_TypeDef *)&hwp_hmailbox->C1EXR)
 
#define HMUTEX_CH2   ((MUTEX_CH_TypeDef *)&hwp_hmailbox->C2EXR)
 
#define L2H_MAILBOX   ((MAILBOX_CH_TypeDef *)LMAILBOX_BASE)
 
#define LMUTEX_CH1   ((MUTEX_CH_TypeDef *)&hwp_lmailbox->C1EXR)
 
#define LMUTEX_CH2   ((MUTEX_CH_TypeDef *)&hwp_lmailbox->C2EXR)
 
#define EPIC   hwp_epic
 
#define LCDC1   hwp_lcdc1
 
#define LCDC2   hwp_lcdc2
 
#define I2C1   hwp_i2c1
 
#define I2C2   hwp_i2c2
 
#define I2C3   hwp_i2c3
 
#define I2C4   hwp_i2c4
 
#define I2C5   hwp_i2c5
 
#define I2C6   hwp_i2c6
 
#define CRC   hwp_crc
 
#define EZIP   hwp_ezip
 
#define DMA1_Channel1   ((DMA_Channel_TypeDef *) &DMA1->CCR1)
 
#define DMA1_Channel2   ((DMA_Channel_TypeDef *) &DMA1->CCR2)
 
#define DMA1_Channel3   ((DMA_Channel_TypeDef *) &DMA1->CCR3)
 
#define DMA1_Channel4   ((DMA_Channel_TypeDef *) &DMA1->CCR4)
 
#define DMA1_Channel5   ((DMA_Channel_TypeDef *) &DMA1->CCR5)
 
#define DMA1_Channel6   ((DMA_Channel_TypeDef *) &DMA1->CCR6)
 
#define DMA1_Channel7   ((DMA_Channel_TypeDef *) &DMA1->CCR7)
 
#define DMA1_Channel8   ((DMA_Channel_TypeDef *) &DMA1->CCR8)
 
#define DMA1_CSELR   ((DMA_Request_TypeDef *) &DMA1->CSELR1)
 
#define DMA2_Channel1   ((DMA_Channel_TypeDef *) &DMA2->CCR1)
 
#define DMA2_Channel2   ((DMA_Channel_TypeDef *) &DMA2->CCR2)
 
#define DMA2_Channel3   ((DMA_Channel_TypeDef *) &DMA2->CCR3)
 
#define DMA2_Channel4   ((DMA_Channel_TypeDef *) &DMA2->CCR4)
 
#define DMA2_Channel5   ((DMA_Channel_TypeDef *) &DMA2->CCR5)
 
#define DMA2_Channel6   ((DMA_Channel_TypeDef *) &DMA2->CCR6)
 
#define DMA2_Channel7   ((DMA_Channel_TypeDef *) &DMA2->CCR7)
 
#define DMA2_Channel8   ((DMA_Channel_TypeDef *) &DMA2->CCR8)
 
#define DMA2_CSELR   ((DMA_Request_TypeDef *) &DMA2->CSELR1)
 

Detailed Description

Copyright (c) 2019 - 2022, Sifli Technology

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form, except as embedded into a Sifli integrated circuit in a product or a software update for such product, must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of Sifli nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  4. This software, with or without modification, must only be used with a Sifli integrated circuit.
  5. Any software provided in binary form under this license must not be reverse engineered, decompiled, modified and/or disassembled.

THIS SOFTWARE IS PROVIDED BY SIFLI TECHNOLOGY "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SIFLI TECHNOLOGY OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ EPIC

#define EPIC   hwp_epic

EPIC instance

◆ EZIP

#define EZIP   hwp_ezip

EZIP instance

◆ H2L_MAILBOX

#define H2L_MAILBOX   ((MAILBOX_CH_TypeDef *)HMAILBOX_BASE)

HCPU2LCPU mailbox instance

◆ HMUTEX_CH1

#define HMUTEX_CH1   ((MUTEX_CH_TypeDef *)&hwp_hmailbox->C1EXR)

HCPU mutex instance channel1

◆ HMUTEX_CH2

#define HMUTEX_CH2   ((MUTEX_CH_TypeDef *)&hwp_hmailbox->C2EXR)

HCPU mutex instance channel2

◆ hwp_epic

#define hwp_epic   ((EPIC_TypeDef *) EPIC_BASE)

EPIC instance

◆ hwp_ezip

#define hwp_ezip   ((EZIP_TypeDef *) EZIP_BASE)

EZIP instance

◆ hwp_gpio1

#define hwp_gpio1   ((GPIO_TypeDef *) GPIO1_BASE)

GPIO1

◆ hwp_gpio2

#define hwp_gpio2   ((GPIO_TypeDef *) GPIO2_BASE)

GPIO2

◆ hwp_hpsys_aon

#define hwp_hpsys_aon   ((HPSYS_AON_TypeDef *) HPSYS_AON_BASE)

HPSYS AON

◆ hwp_lpsys_aon

#define hwp_lpsys_aon   ((LPSYS_AON_TypeDef *) LPSYS_AON_BASE)

LPSYS AON

◆ hwp_pinmux1

#define hwp_pinmux1   ((HPSYS_PINMUX_TypeDef *) PINMUX1_BASE)

PINMUX1

◆ hwp_pinmux2

#define hwp_pinmux2   ((LPSYS_PINMUX_TypeDef *) PINMUX2_BASE)

PINMUX2

◆ L2H_MAILBOX

#define L2H_MAILBOX   ((MAILBOX_CH_TypeDef *)LMAILBOX_BASE)

LCPU2HCPU mailbox instance

◆ LMUTEX_CH1

#define LMUTEX_CH1   ((MUTEX_CH_TypeDef *)&hwp_lmailbox->C1EXR)

LCPU mutex instance channel1

◆ LMUTEX_CH2

#define LMUTEX_CH2   ((MUTEX_CH_TypeDef *)&hwp_lmailbox->C2EXR)

LCPU mutex instance channel2