I2S bus configure structure definition. More...

#include <bf0_hal_i2s.h>

Data Fields
uint8_t	bus_dw

uint8_t	data_dw

uint8_t	slave_mode

uint8_t	track

uint8_t	chnl_sel

uint8_t	lrck_invert

uint32_t	sample_rate

uint32_t	bclk

uint8_t	vol

uint8_t	balance_en

uint8_t	balance_vol

uint8_t	extern_intf

uint8_t	pcm_dw

uint8_t	clk_div_index

CLK_DIV_T *	clk_div

Detailed Description

I2S bus configure structure definition.

Field Documentation

◆ balance_en

uint8_t I2S_CFG_T::balance_en

0 balance disable, 1 right channel adjust, 2 left channel adjust

◆ balance_vol

uint8_t I2S_CFG_T::balance_vol

when balance_en=1, 1 ~ 15, 1=-1.5db, 2=-3db ... 14=-21db, 15=mute

◆ bclk

uint32_t I2S_CFG_T::bclk

I2S BCLK

◆ bus_dw

uint8_t I2S_CFG_T::bus_dw

I2S bus data width 8, 16, 24 32 ...

◆ chnl_sel

uint8_t I2S_CFG_T::chnl_sel

0 noral, 5 left/write switch , 0xa left right average

◆ clk_div_index

uint8_t I2S_CFG_T::clk_div_index

clock divder index(for txrx_clk_div), base on sample rate

◆ data_dw

uint8_t I2S_CFG_T::data_dw

output data width, only support 8 or 16

◆ extern_intf

uint8_t I2S_CFG_T::extern_intf

0 use internal apb memory, 1 use external interface

◆ lrck_invert

uint8_t I2S_CFG_T::lrck_invert

for standard I2S, set lrck_pol to 0,for Left/Right Justified, set lrck_pol to 1

◆ pcm_dw

uint8_t I2S_CFG_T::pcm_dw

For I2S rx/tx data width , related with peripheral

◆ sample_rate

uint32_t I2S_CFG_T::sample_rate

Sample rate

◆ slave_mode

uint8_t I2S_CFG_T::slave_mode

0 master mode, 1 slave mode.

◆ track

uint8_t I2S_CFG_T::track

1 mono, 0s stereo

◆ vol

uint8_t I2S_CFG_T::vol

0 ~ 15, 0=+6db, 4=0db, 14=-15db, 15=mute

The documentation for this struct was generated from the following file:

drivers/include/bf0_hal_i2s.h

Data Fields